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HCS112MS
September 1995
Radiation Hardened Dual JK Flip-Flop
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW
CP1 1 KA 2 JA 3 SA 4 QA 5 16 VCC 15 RA 14 RB 13 CPB 12 KB 11 JB 10 SB 9 QB
Features
* 3 Micron Radiation Hardened SOS CMOS * Total Dose 200K RAD (Si) * SEP Effective LET No Upsets: >100 MEV-cm2/mg * Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ) * Dose Rate Survivability: >1 x 1012 RAD (Si)/s
* Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse * Latch-Up Free Under Any Conditions * Military Temperature Range: -55oC to +125oC * Significant Power Reduction Compared to LSTTL ICs * DC Operating Voltage Range: 4.5V to 5.5V * Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min * Input Current Levels Ii 5A at VOL, VOH
QA 6 QB 7 GND 8
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C TOP VIEW
CP1 KA JA SA QA QA QB GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RA RB CPB KB JB SB QB
Description
The Intersil HCS112MS is a Radiation Hardened dual JK flip-flop with set and reset. The output changes state on the negative going transition of the clock pulse. Set and reset are accomplished asynchronously by a logic low input level. The HCS112MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS112MS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBER HCS112DMSR HCS112KMSR HCS112D/Sample HCS112K/Sample HCS112HMSR TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC +25oC +25oC +25oC SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample Sample Die PACKAGE 16 Lead SBDIP 16 Lead Ceramic Flatpack 16 Lead SBDIP 16 Lead Ceramic Flatpack Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
Spec Number File Number
11
518830 3558.1
DB NA
HCS112MS Functional Diagram
5 (9) CL Q P 3(11) J CL P N 2(12) K 4(10) S 15(14) R 1(13) CL CP CL CL N CL CL P N CL CL P N CL 6 (7) Q
TRUTH TABLE INPUTS S L H L H H H H H R H L L H H H H H H CP X X X J X X X L H L H X K X X X L L H H X H L Toggle No Change Q H L H* No Change L H OUTPUTS Q L H H*
H = High Steady State, L = Low Steady State, X = Immaterial, = High-to-Low Transition * Output States Unpredictable if S and R Go High Simultaneously after Both being Low at the Same Time
Spec Number 12
518830
Specifications HCS112MS
Absolute Maximum Ratings
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .25mA (All Voltage Reference to the VSS Terminal) Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance JA JC SBDIP Package. . . . . . . . . . . . . . . . . . . . 73oC/W 24oC/W Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC
CAUTION: As with all semiconductors, stress listed under "Absolute Maximum Ratings" may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under "Electrical Performance Characteristics" are the only conditions recommended for satisfactory device operation.
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . 100ns/V Max Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . VCC to 70% of VCC Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2, 3 Output Current (Sink) IOL VCC = 4.5V, VIH = 4.5V, VOUT = 0.4V, VIL = 0V, (Note 2) VCC = 4.5V, VIH = 4.5V, VOUT = VCC - 0.4V, VIL = 0V, (Note 2) VCC = 5.5V, VIH = 3.85V, IOL = 50A, VIL = 1.65V VCC = 4.5V, VIH = 3.15V, IOL = 50A, VIL = 1.35V Output Voltage High VOH VCC = 5.5V, VIH = 3.85V, IOH = -50A, VIL = 1.65V VCC = 4.5V, VIH = 3.15V, IOH = -50A, VIL = 1.35V Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND 1 2, 3 1 2, 3 1, 2, 3 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC, +125oC, -55oC MIN 4.8 4.0 -4.8 -4.0 MAX 20 400 0.1 UNITS A A mA mA mA mA V
PARAMETER Supply Current
SYMBOL ICC
(NOTE 1) CONDITIONS VCC = 5.5V, VIN = VCC or GND
Output Current (Source)
IOH
Output Voltage Low
VOL
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
1, 2, 3
+25oC, +125oC, -55oC
VCC -0.1 VCC -0.1
-
V
1, 2, 3
+25oC, +125oC, -55oC
-
V
1 2, 3
+25oC +125oC, -55oC +25oC, +125oC, -55oC -
0.5 5.0 -
A A -
Noise Immunity Functional Test NOTES:
FN
VCC = 4.5V, VIH = 3.15V, VIL = 1.35V (Note 3)
7, 8A, 8B
1. All voltages referenced to device GND. 2. Force/Measure Functions may be interchanged. 3. For functional tests, VO 4.0V is recognized as a logic "1", and VO 0.5V is recognized as a logic "0".
Spec Number 13
518830
Specifications HCS112MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS LIMITS TEMPERATURE MIN MAX UNITS
PARAMETER
SYMBOL
(NOTES 1, 2) CONDITIONS
PROPAGATION DELAY CP to Q, Q TPHL, TPLH TPHL VCC = 4.5V, VIH = 4.5V, VIL = 0V VCC = 4.5V, VIH = 4.5V, VIL = 0V VCC = 4.5V, VIH = 4.5V, VIL = 0V VCC = 4.5V, VIH = 4.5V, VIL = 0V VCC = 4.5V, VIH = 4.5V, VIL = 0V 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC 2 2 2 2 2 2 2 2 2 2 28 35 27 33 27 33 26 32 26 32 ns ns ns ns ns ns ns ns ns ns
S to Q
S to Q
TPLH
R to Q
TPHL
R to Q
TPLH
NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Capacitance Power Dissipation Input Capacitance SYMBOL CPD CONDITIONS VCC = 5.0V, VIH = 5.0V, VIL = 0.0V, f = 1MHz VCC = 5.0V, VIH = 5.0V, VIL = 0.0V, f = 1MHz VCC =5.0V, VIH = 5.0V, VIL = 0.0V, f = 1MHz VCC = 4.5V, VIH = 4.5V, VIL = 0.0V, VCC = 4.5V, VIH = 4.5V, VIL = 0.0V, VCC = 4.5V, VIH = 4.5V, VIL = 0.0V, VCC = 4.5V, VIH = 4.5V, VIL = 0.0V, VCC = 4.5V, VIH = 4.5V, VIL = 0.0V, VCC = 4.5V , VIH = 4.5V, VIL = 0.0V, NOTES 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC MIN 16 24 16 24 0 0 16 24 30 20 1 1 MAX 15 45 10 10 10 10 15 22 UNITS pF pF pF pF ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns
CIN
Output Capacitance
COUT
Pulse Width Time CP, R, S Setup Time J, K to CP Hold Time J, K to CP
TW
TSU
TH
Removal Time S to CP, R to CP Max Operating Frequency Output Transition Time NOTE:
TREM
FMAX
TTHL, TTLH
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
Spec Number 14
518830
Specifications HCS112MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS 200K LIMITS RAD PARAMETER Supply Current Output Current (Sink) SYMBOL ICC IOL (NOTES 1, 2) CONDITIONS VCC = 5.5V, VIN = VCC or GND VCC = VIH = 4.5V, VIL = 0.0V, VOUT = 0.4V VCC = VIH = 4.5V, VIL = 0.0V, VOUT = VCC -0.4V VCC = 5.5V, VIH = 3.85V, VIL = 1.65V, IOL = 50A VCC = 4.5V, VIH = 3.15V, VIL = 1.35V, IOL = 50A Output Voltage High VOH VCC = 5.5V, VIH = 3.85V, VIL =1.65V, IOH = -50A VCC = 4.5V, VIH = 3.15V, VIL =1.35V, IOH = -50A Input Leakage Current Noise Immunity Functional Test PROPAGATION DELAY CP to Q, Q TPHL, TPLH TPLH TPHL TPHL TPLH VCC = 4.5V +25oC 2 35 ns IIN FN VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIH =3.15V, VIL = 1.35V, (Note 3) TEMPERATURE +25oC +25oC MIN 4.0 MAX 0.4 UNITS mA mA
Output Current (Source) Output Voltage Low
IOH
+25oC
-4.0
-
mA
VOL
+25oC
-
0.1
V
+25oC
-
0.1
V
+25oC
VCC -0.1 VCC -0.1
-
V
+25oC
-
V
+25oC +25oC -
5 -
A -
S to Q S to Q R to Q R to Q NOTES:
VCC = 4.5V VCC = 4.5V VCC = 4.5V VCC = 4.5V
+25oC +25oC +25oC +25oC
2 2 2 2
33 33 32 32
ns ns ns ns
1. All voltages referenced to device GND. 2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V. 3. For functional tests VO 4.0V is recognized as a logic "1", and VO 0.5V is recognized as a logic "0".
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC) GROUP B SUBGROUP 5 5
PARAMETER ICC IOL/IOH
DELTA LIMIT 6A -15% of 0 Hour
Spec Number 15
518830
Specifications HCS112MS
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTE: 1. Alternate Group A testing in accordance with Method 5005 of MIL-STD-883 may be exercised. METHOD 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 Sample/5005 Sample/5005 Sample/5005 Sample5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 7, 9 Subgroups 1, 2, 3, 9, 10, 11 ICC, IOL/H READ AND RECORD ICC, IOL/H ICC, IOL/H ICC, IOL/H
TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 NOTE: 1. Except FN test which will be performed 100% Go/No-Go. TEST METHOD 5005 PRE RAD 1, 7, 9 POST RAD Table 4 READ AND RECORD PRE RAD 1, 9 POST RAD Table 4 (Note 1)
TABLE 8. STATIC BURN-IN AND DYNAMIC BURN-IN TEST CONNECTIONS OSCILLATOR OPEN GROUND 1/2 VCC = 3V 0.5V VCC = 6V 0.5V 50kHz 25kHz
STATIC BURN-IN I TEST CONNECTIONS (Note 1) 5, 6, 7, 9 1 - 4, 8, 10 - 15 16 -
STATIC BURN-IN II TEST CONNECTIONS (Note 1) 5, 6, 7, 9 8 1 - 4, 10 - 16 -
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2) NOTES: 1. Each pin except VCC and GND will have a resistor of 10K 5% for static burn-in. 2. Each pin except VCC and GND will have a resistor of 1K 5% for dynamic burn-in. 8 5, 6, 7, 9 2, 3, 4, 10, 11, 12, 14, 15, 16 1, 13 -
TABLE 9. IRRADIATION TEST CONNECTIONS OPEN 5, 6, 7, 9 GROUND 8 VCC = 5V 0.5V 1 - 4, 10 - 16
NOTE: Each pin except VCC and GND will have a resistor of 47K 5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number 16
518830
HCS112MS Intersil Space Level Product Flow - `MS'
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Interim Electrical Test 2 (T2) 100% Delta Calculation (T0-T2) 100% PDA 1, Method 5004 (Notes 1and 2) 100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or Equivalent, Method 1015 100% Interim Electrical Test 3 (T3) 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 2) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic, Method 2012 (Note 3) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) 100% Data Package Generation (Note 5)
NOTES: 1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Data Package Contents: * Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). * Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. * GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. * X-Ray report and film. Includes penetrometer measurements. * Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). * Lot Serial Number Sheet (Good units serial number and lot number). * Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. * The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
Spec Number 17
518830
HCS112MS Propagation Delay Timing Diagram and Load Circuit
VIH VS VSS TPLH TPHL VOH VS VOL INPUT CP VIH VS TW OUTPUT TSU VIL TH VS INPUT
Pulse Width, Setup, Hold Timing Diagram Negative Edge Trigger and AC Load Circuit
INPUT VIH TW
Transition Timing Diagram
VOH TTLH 80% VOL 20% 80% 20% TTHL
VIL TH = HOLD TIME TSU = SETUP TIME TW = PULSE WIDTH
OUTPUT
DUT CL
TEST POINT RL CL = 50pF RL = 500
DUT CL
TEST POINT RL CL = 50pF RL = 500
VOLTAGE LEVELS PARAMETER VCC VIH VS VIL GND HCS 4.50 4.50 2.25 0 0 UNITS V V V V V PARAMETER VCC VIH VS VIL GND
VOLTAGE LEVELS HCTS 4.50 4.50 2.25 0 0 UNITS V V V V V
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
Spec Number 18
518830
HCS112MS Die Characteristics
DIE DIMENSIONS: 89 x 88 mils 2.25 x 2.24mm METALLIZATION: Type: SiAl Metal Thickness: 11kA 1kA GLASSIVATION: Type: SiO2 Thickness: 13kA 2.6kA WORST CASE CURRENT DENSITY: <2.0 x 105A/cm2 BOND PAD SIZE: 100m x 100m 4 mils x 4 mils
Metallization Mask Layout
HCS112MS
KA (2) CP1 (1) VCC (16)
JA (3)
(15) RA
SA (4)
(14) RB
QA (5) (13) CPB
QA (6)
(12) KB
(11) JB QB (7)
(8) GND
(9) QB
(10) SB
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCS112 is TA14341A.
Spec Number 19
518830

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